Field of the Invention
The present invention relates to a double-RESURF-type lateral diffused MOSFET (LDMOS) transistor having a stacked oxide/dielectric “bump” gate support structure and associated self-aligned N-drift and P-surf implants, and to a method for fabricating such double-RESURF LDMOS transistors.
Related Art
RESURF (Reduced Surface Field) technology is one of the most widely used methods in Power management applications for providing high voltage (HV) transistors exhibiting both a high break down voltage (BV) and a low specific resistance (RDSON). The RESURF technique is a set up in an LDMOS transistor that includes a vertical PN junction in which its depletion layer extends upward and reaches the surface before breakdown occurs in the horizontal direction. As a result the surface electric field is reduced significantly. The resulting shape of the lateral electric field in this case (RESURF) would be a trapezoidal shape, contrary to the standard, conventional LDMOS case where the electric field has a triangular shape. The trapezoidal shape of the electric field translates itself to an advantage of higher voltage for the same doping density which translates to the same RDSON for a higher BV. This is the reason that the RESURF technique gives the very best trade-off between RDSON and BV. One good side effect of the RESURF technique is that it involves forming laterally diffused metal oxide semiconductor (LDMOS) transistors in a relatively thin layer of epitaxial (Epi) layer, which is less time consuming to produce, and the resulting “RESURF LDMOS” transistors having a much higher BV and lower RDSON than conventional vertical power transistors. The thinner Epi thickness is due to the need to reach with the depletion layer all the way to the upper Epi surface, which requires a relatively thin Epi.
FIG. 6 is a cross sectional view of a conventional RESURF LDMOS transistor 10, which includes P+ substrate 11, P− epitaxial layer 12, deep p-well region 13, P+ backgate contact 14, N+ source region 15, N type reduced surface field region 16, N+ drain contact region 17, gate oxide layer 18, field oxide regions 19-1 and 19-2 and gate electrode POLY-1. Field oxide regions 19-1 and 19-2 are formed simultaneously by conventional local oxidation of silicon (LOCOS) or poly-buffered LOCOS (PBL). Field oxide region 19-2 provides electrical isolation between LDMOS transistor 10 and other devices (not shown) fabricated in the same substrate. Field oxide region 19-2 must be relatively thick to provide such isolation. For example, field oxide region 19-2 typically has a thickness of about 5000 Angstroms or more (depending on the technology node). Because field oxide regions 19-1 and 19-2 are thermally grown, half of these oxide regions are grown underneath the silicon surface. Thus, field oxide regions 19-1 and 19-2 extend into the silicon surface to a depth of about 2500 Angstroms or more. Because they are fabricated at the same time, field oxide regions 19-1 and 19-2 have the same thickness. Field oxide region 19-1 is thick enough to protect gate oxide layer 18 from high electric fields that result from voltages applied to drain contact region 17. That is, the field oxide region 19-1 is sufficiently thick under polysilicon gate electrode POLY-1 where the diffusion region 16 extends between the channel edge and the drain contact region 17. LDMOS transistor 10 is described in more detail in U.S. Pat. No. 6,483,149 to Mosher et al.
In high voltage and power applications, it is desirable to minimize the on-resistance RDSON of LDMOS transistor 10, such that the switch area and power dissipation associated with this transistor 10 is minimized. However, current flowing through LDMOS transistor 10 is forced to bypass the field oxide region 19-1, thereby resulting in a relatively high RDSON. That is, the current flowing through LDMOS transistor 10 must flow deep within the silicon, along the relatively long path that exists under field oxide region 19-1.
FIG. 7 is a cross sectional view of another conventional LDMOS transistor 20, wherein field oxide regions 19-1 and 19-2 are replaced by shallow trench isolation (STI) regions 29-1 and 29-2, and polysilicon gate electrode POLY-1 is replaced by polysilicon gate electrode POLY-2. STI regions 29-1 and 29-2 are formed simultaneously by conventional methods (i.e., etching trenches in the substrate, and then filling the trenches with dielectric material). STI region 29-2 provides electrical isolation between LDMOS transistor 20 and other devices (not shown) fabricated in the same substrate. In general, STI region 29-2 extends deeper below the surface of the substrate in comparison to field oxide region 19-2, as trench isolation is almost completely below the silicon surface. Thus, in the described example, STI region 29-2 usually has a depth of about 3500 Angstroms. Because they are fabricated at the same time, STI regions 29-1 and 29-2 have the same depth (e.g., 3500 Angstroms). The large depth of STI region 29-1 causes LDMOS transistor 20 to exhibit higher on-resistance than LDMOS transistor 10. In addition, the sharp corners typical of STI region 29-1 (compared to the smooth profile at the LOCOS bird's beak region) locally increases the electric field at those corners, which results in rapid hot carrier degradation and lower breakdown voltage within LDMOS transistor 20.
Another issue associated with the use of RESURF LDMOS transistors in high current applications involving inductive loads is that unwanted current injection to the substrate is generated by way of a parasitic bipolar transistor formed by the body/deep-N-well/substrate regions of the RESURF LDMOS transistor. To avoid the excess minority injection causing this parasitic bipolar, a common practice is to use a technique in which an N+ buried layer (NBL) is formed under the entire deep-N-well region in which the LDMOS transistor is formed (i.e., in the region where the the epitaxial layer meets the base underlying substrate). Although such N+ Buried layer architecture LDMOS transistors are superior to earlier LDMOS transistors in high current applications, the NBL acts to reduce the BV, and also results in higher RDSON for a given breakdown voltage.
FIG. 8 is a cross sectional view of a conventional double-RESURF NBL architecture LDMOS transistor 30 that illustrates a recent methodology that takes advantage of the NBL isolation while maintaining high BV by providing a P+ buried layer (P-Well) in the epitaxial layer between the NBL and the deep N-well located below the LOCOS gate oxide and containing the drain portion of the LDMOS. The double RESURF architecture is an extension to the RESURF case (described above) in which an electrical field shape is tailored to hold optimal maximal BV. This technique including depleting the drift layer from two directions, contrary to regular RESURF which does not necessary involves depletion from two sides. FIG. 8 shows an example of depleting from two sides that involves depleting from the bottom using the buried P-well, and depleting from the top by causing the gate to “climb” over the oxide that forms the extended drain. The resulting electrical field would be closer to the ideal rectangular shape than in the case of single RESURF (which involves depletion from one side only). In the double-RESURF case the area under the electric field distance curve will be larger and hence would carry a larger BV for a given RDSON. The P-Well serves to gain back the desired high BV for devices having smaller geometries by inducing depletion in the drift region of the epitaxial layer, and is formed by implanting ions of an P-type material (e.g., Boron (B) in the semiconductor substrate of the device) over a portion of the NBL, and then up-diffusing the P-type ions into an epitaxial layer to provide the desired position of the P-well between the NBL and a N-well containing the drain portion of the LDMOS.
A problem with the conventional double-RESURF approach illustrated in FIG. 8 is that it requires the use of a complicated boron implant process that utilizes extra high energy from the top of the device to be buried below the deep N-well, as disclosed in “A Double-RESURF LDMOS With Drain Profile Engineering for Improved ESD Robustness” by V Parthasarathy Et Al, in IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 4, APRIL 2002 p212. The Boron, which forms the PBL, is implanted with the Antimony (Sb) that forms the NBL, and diffuses faster than the Sb, and so desirably forms the PBL between the deep N-well and the NBL. However, the process requires the formation of two separate masks having specific thicknesses in order to effectively implant the Boron and Sb at the proper dosages and depths such that they form the required PBL and NBL regions.
Another problem associated with the conventional double-RESURF approach is that it is very difficult to scale the implant process for higher voltages. That is, in the prior art case to scale the voltage deeper more energetic implant is needed and is also limited.
Yet another problem associated with the conventional double-RESURF approach is that patterning the P-well below the N-well (extended drain implant) is either restricted to the layout of the extended drain or requires an extra mask. That is, it is important to be able to pattern the PBL (independently from the NBL) in order to optimize the BV vs. RDSON characteristics of the cell.
What is needed is an improved double-RESURF LDMOS transistor addressing the problems set forth above. What is also needed is a cost effective and reliable method for generating such improved double-RESURF LDMOS transistors, wherein the method requires minimal modifications to a standard process flow.